Jitter, Noise, and Signal Integrity at High-Speed.pdf
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1、 User name: CSU San Diego Book: Jitter, Noise, and Signal Integrity at High-Speed No part of any chapter or book may be reproduced or transmitted in any form by any means without the prior written permission for reprints and excerpts from the publisher of the book or chapter. Redistribution or other
2、 use that violates the fair use privilege under U.S. copyright laws (see 17 USC107) or that otherwise violates these Terms of Service is strictly prohibited. Violators will be prosecuted to the full extent of U.S. Federal and Massachusetts laws. Information Theory Computer Science Mike Peng Li Prent
3、ice Hall Jitter, Noise, and Signal Integrity at High-Speed Copyright An Imprint of Pearson Education Many of the designations used by manufacturers and sellers to distinguish their products are claimed as trademarks. Where those designations appear in this book, and the publisher was aware of a trad
4、emark claim, the designations have been printed with initial capital letters or in all capitals. The author and publisher have taken care in the preparation of this book, but they make no expressed or implied warranty of any kind and assume no responsibility for errors or omissions. No liability is
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7、ing-in-Publication Data: Li, Mike Peng. Jitter, noise, and signal integrity at high-speed / Mike Peng Li. p. cm. ISBN 0-13-242961-6 (hardback : alk. paper) 1. TelecommunicationTraffic. 2. High performance computing. I. Title. TK5102.985.L56 2007 621.382dc22 2007036914 Copyright 2008 Pearson Educatio
8、n, Inc. All rights reserved. Printed in the United States of America. This publication is protected by copyright, and permission must be obtained from the publisher prior to any prohibited reproduction, storage in a retrieval system, or transmission in any form or by any means, electronic, mechanica
9、l, photocopying, recording, or likewise. For information regarding permissions, write to: Pearson Education, Inc. Rights and Contracts Department 501 Boylston Street, Suite 900 Boston, MA 02116 URL http:/ ISBN-13: 978-0-13-242961-0 Text printed in the United States on recycled paper at Courier in We
10、stford, Massachusetts. First printing: November 2007 Credits Editor-in-Chief Mark Taub Publishing Partner Bernard Goodwin Managing Editor Gina Kanouse Project Editor Jovana San Nicolas-Shirley Copy Editor Gayle Johnson Indexer Lisa Stumpf Proofreader Water Crest Publishing Editorial Assistant Michel
11、le Housley Cover Designer Louisa Adair Composition ContentWorks Graphics Jake McFarland Laura Robbins Dedication To Mercia, Eric, George, and my parents. User name: CSU San Diego Book: Jitter, Noise, and Signal Integrity at High-Speed No part of any chapter or book may be reproduced or transmitted i
12、n any form by any means without the prior written permission for reprints and excerpts from the publisher of the book or chapter. Redistribution or other use that violates the fair use privilege under U.S. copyright laws (see 17 USC107) or that otherwise violates these Terms of Service is strictly p
13、rohibited. Violators will be prosecuted to the full extent of U.S. Federal and Massachusetts laws. Information Theory Computer Science Mike Peng Li Prentice Hall Jitter, Noise, and Signal Integrity at High-Speed Prentice Hall Modern Semiconductor Design Series James R. Armstrong and F. Gail Gray VHD
14、L Design Representation and Synthesis Mark Gordon Arnold Verilog Digital Computer Design: Algorithms into Hardware Jayaram Bhasker A VHDL Primer, Third Edition Mark D. Birnbaum Essential Electronic Design Automation (EDA) Eric Bogatin Signal Integrity: Simplified Douglas Brooks Signal Integrity Issu
15、es and Printed Circuit Board Design Ken Coffman Real World FPCA Design with Verilog Alfred Crouch Design-for-Test for Digital ICs and Embedded Core Systems Dennis Derickson and Marcus Mller (Editors) Digital Communications Test and Measurement Greg Edlund Timing Analysis and Simulation for Signal In
16、tegrity Engineers Daniel P. Foty MOSFET Modeling with SPICE: Principles and Practice Tom Granberg Handbook of Digital Techniques for High-Speed Design Nigel Horspool and Peter Gorman The ASIC Handbook William K. Lam URL http:/ Hardware Design Verification: Simulation and Formal Method-Based Approach
17、es Mike Peng Li Jitter, Noise, and Signal Integrity at High-Speed Farzad Nekoogar and Faranak Nekoogar From ASICs to SOCs: A Practical Approach Farzad Nekoogar Timing Verification of Application-Specific Integrated Circuits (ASICs) Samir Palnitkar Design Verification with David Pellerin and Scott Th
18、ibault Practical FPCA Programming in C Christopher T. Robertson Printed Circuit Board Designers Reference: Basics Chris Rowen Engineering the Complex SOC Madhavan Swaminathan and A. Ege Engin Power Integrity Modeling and Design for Semiconductors and Systems Wayne Wolf FPCA-Based System Design Wayne
19、 Wolf Modern VLSI Design: System-on-Chip Design, Third Edition Bob Zeidman Verilog Designers Library User name: CSU San Diego Book: Jitter, Noise, and Signal Integrity at High-Speed No part of any chapter or book may be reproduced or transmitted in any form by any means without the prior written per
20、mission for reprints and excerpts from the publisher of the book or chapter. Redistribution or other use that violates the fair use privilege under U.S. copyright laws (see 17 USC107) or that otherwise violates these Terms of Service is strictly prohibited. Violators will be prosecuted to the full e
21、xtent of U.S. Federal and Massachusetts laws. Information Theory Computer Science Mike Peng Li Prentice Hall Jitter, Noise, and Signal Integrity at High-Speed Preface Moores Law continues to guide the semiconductor technology road map. As the feature size of integrated circuits (ICs) reaches 65 nm t
22、oday, and moves to 45, 32, and 22 nm in the near future, it will give IC systems more functionality and data-handling capability. A complex and functionality-rich system needs fast input/output (I/O) to be efficient. As a result, we see that the I/O speed keeps increasing as the number of transistor
23、s keeps increasing for advanced IC systems. Although decreasing feature size and increasing I/O speed enable better system capability and performance, they also introduce technological challenges. One of the most important challenges is jitter as I/O speed increases, because the unit interval (UI),
24、the total available jitter budget for a link, must decrease accordingly to ensure a reasonable bit error rate (BER) for a link system. Another very important challenge as the feature size decreases is to constrain the power density and power consumption within limits, implying that low-power design
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